DS200UCPBG6AFB - I/O Engine CPU Board

SPECIFICATIONS:

Part Number: DS200UCPBG6AFB
Manufacturer: General Electric
Series: Mark V LM
Product Type: I/O Engine CPU Board
Power Requirements: +5 V dc
Repair: 3-7 Day
Availability: In Stock
Country of Origin: United States
Manual: GEH-6153

FUNCTIONAL DESCRIPTION:

DS200UCPBG6AFB is an I/O Engine CPU Board manufactured and designed by General Electric as part of the Mark V LM Series used in GE Speedtronic Control Systems. The IO Engine CPU board (UCPB) is the daughterboard mounted on STCA in the IO Engines. The UCPB board contains an 80486DX processor (CPU), a single inline memory module (SIMM) socket with dynamic random access memory (DRAM), flash erasable programmable read-only memory (EPROM) with ROM BIOS, I/O mapped flash EPROM, two RS-232 serial ports, and an ARCNET driver. One UCPB is installed in each of the IO Engines: , , and . A PCM daughterboard is installed on the UCPB in for serial communication with FMVED motor controllers.

The UCPB processor packages the analog and digital IO information and broadcasts it on the COREBUS. The packets are broadcast according to a task schedule. Packets are sets of information grouped according to need and then transmitted for use by other devices. Critical information is broadcast in a fast packet at 100 Hz or every 10 ms, while less critical information is broadcast in ìslow packetsî, which are broadcast at a slower rate than 100 Hz.

UCPB CONFIGURATION:

Hardware: There are three hardware jumpers located on the UCPB board. JP1 and JP3 are used for factory tests. JP2 selects the 486 local bus speed. Initiating a hard re-boot by using the power on/off switch for the specific IO core located in the core is the recommended method for rebooting. The DIP switches are used to set the COREBUS address for a given IO Engine. Refer to Appendix A for information on the hardware jumper settings for this board. The hardware jumpers on the PCM need to be configured as described in the FMVED commissioning guide only if serial communication with a GE Industrial Systems motor controller is required.

Software: The software product for the IO Engine is called TMIA and contains the IO configuration data for the FMVED serial download software, WATT/VAR input, and three pulse rate inputs.

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FREQUENTLY ASKED QUESTIONS:

What is an I/O Engine CPU Board?

An I/O Engine CPU Board is a hardware component that integrates a central processing unit (CPU) with input/output (I/O) interfaces. It serves as a crucial part of a system, facilitating communication between the CPU and various peripherals.

What is the role of an I/O Engine CPU Board in a system?

The I/O Engine CPU Board plays a key role in managing and controlling data transfer between the central processing unit and external devices. It handles input and output operations, ensuring seamless communication within the system.

What types of peripherals can be connected to an I/O Engine CPU Board?

I/O Engine CPU Boards support a wide range of peripherals, including but not limited to storage devices, network interfaces, USB devices, and various sensors. The specific compatibility depends on the board's design and specifications.