DS200TCDAH1BHF - Digital I/O Board

SPECIFICATIONS:

Part Number: DS200TCDAH1BHF
Manufacturer: General Electric
Series: Mark V LM
Product Type: Digital I/O Board
Power Requirements: +5 V dc, 6 A
Number of relay channels: 32
Power supply voltage: 28 V dc
Mounting: DIN-rail mounting
Technology: Surface mount
Operating temperature: -30 to +65°C
Size: 15.9 cm high x 17.8 cm
Repair: 3-7 Day
Availability: In Stock
Country of Origin: United States
Manual: GEI-100182B

FUNCTIONAL DESCRIPTION:

DS200TCDAH1BHF is a Digital I/O Board manufactured and designed by General Electric as part of the Mark V LM Series used in GE Speedtronic Control Systems. The Digital I/O Board (TCDA) resides within the digital I/O cores , , and, if applicable, . It processes digital contact input signals from the DTBA and DTBB terminal boards and contact output signals (relay/solenoid) from the TCRA boards. These signals are transmitted via the IONET to the TCQC board in and , or to the CTBA terminal board in when is present. The TCDA board features eight hardware jumpers for various configurations, including IONET termination resistors, network ID settings, and enabling a stall timer, while J1 and J8 are reserved for factory testing. Designed for reliable performance in demanding environments, it plays a critical role in turbine control by managing start-up, shutdown, and operational safety. Configuration and maintenance details are accessible through system documentation, including Appendix A and the operator interface.

TCDA CONFIGURATION:

HARDWARE: The TCDA board includes eight hardware jumpers, each serving specific functions. J1 and J8 are reserved for factory testing, while J2 and J3 manage IONET termination resistors. Jumpers J4, J5, and J6 set the board's IONET ID, and J7 activates the stall timer. For detailed settings, refer to Appendix A and the hardware jumper screen in the operator interface.

TCDA CONNECTORS:

• JP: Distributes power from the TCPS board in the R1, R2, and R5 cores to the Q11, Q21, and Q51 cores, respectively.

• JQ: Connects to the JQR socket on the DTBA board, transmitting contact input signals from the DTBA board to the TCDA board.

• JR: Connects to the JRR socket on the DTBB board, conveying contact input signals from the DTBB board to the TCDA board.

• JO1: Transmits contact output (relay/solenoid) signals to the TCRA board in location four. It is not utilized in Q11, as the relays in location 4 are directly controlled by TCQE in R1.

• JO2: Transmits contact output (relay/solenoid) signals to the TCRA board in location five.

• JX1: This is a shielded twisted pair cable for IONET signals. The TCDA board in the QD1 core sends signals to the JX2 connection on the TCEA board in location five of the C core.

• JX2: Used for the same function as JX1. Either JX1 or JX2 can be employed for this purpose.

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FREQUENTLY ASKED QUESTIONS:

How is the IONET ID assigned to the TCDA board?

The IONET ID is set using the hardware jumpers J4, J5, and J6. Each combination corresponds to a unique ID that allows the board to communicate properly within the system.

What is the purpose of the stall timer enabled by J7?

The stall timer monitors the system's operation and triggers safety mechanisms if abnormal conditions, such as unresponsive components, are detected.

How are input signals validated by the TCDA board?

The board uses internal diagnostics to validate digital inputs, ensuring signal integrity and proper operation before relaying them to other components.