DS200PANAG1ADD - ARCNET LAN Driver Board

DS200PANAG1ADD - ARCNET LAN Driver Board DS200PANAG1ADD - ARCNET LAN Driver Board

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SPECIFICATIONS

Part No.: DS200PANAG1ADD
Manufacturer: General Electric
Country of Manufacture: United States of America (USA)
Product Type: ARCNET LAN Driver Board
Availability: In Stock
Series: Mark V

Functional Description

DS200PANAG1ADD is an ARCNET LAN Driver Board developed by GE. It is a part of the Mark V control system. LAN Driver Board (PANA) facilitates ARCNET communication specifically designed for COREBUS and Stage Link functionalities. Positioned as a daughterboard on the LBC586P board within the system, the board connects to the AAHA boards via its APL and BPL connectors. Data transmission occurs through these connectors, enabling seamless communication between the PANA board and the AAHA boards.

Features

  • The board further interfaces with the Control Engine LBC586P processor board through its P1 and P2 bus connectors. These connections ensure efficient data transfer and synchronization with the main processor board, facilitating coordinated operations within the system.
  • A single board is installed at location 1 within the system, enhancing connectivity and operational efficiency by managing ARCNET communications critical for COREBUS and Stage Link functionalities.

Hardware Configuration

  • The board utilizes four switches to establish ARCNET addresses specifically for the R core's COREBUS and Stage Link functionalities. These switches are allocated as follows: two for channel A (Stage Link) and two for channel B (COREBUS). Additionally, hardware jumpers are employed to determine the interrupt, I/O address, and memory address for each ARCNET channel. These settings are pre-defined during manufacturing and are integral to the internal software configurations of the board.
  • When replacing boards, it is imperative to ensure that the hardware jumper settings match those of the old board. This verification guarantees consistency in ARCNET address allocation and operational parameters across the system. For detailed instructions on configuring hardware jumpers.

Software Configuration

  • Unlike hardware settings, the board does not involve any software configuration. Its functionality relies solely on the predetermined hardware settings established via switches and jumpers. This streamlined approach simplifies maintenance and operational setup, ensuring reliability and stability in ARCNET communications for the R core's operations. 

The WOC team is always available to help you with your Mark V requirements. For more information, please contact WOC.

Frequently Asked Questions

What is DS200PANAG1ADD?
It is an ARCNET LAN driver board developed by GE under the Mark V series.

What is the purpose of APL on the board?
APL serves as the ARCNET communication link specifically to the AAHA1 board. It facilitates data exchange and communication protocols between the board and the AAHA1 board, enabling seamless integration and operation within the R core system.

What role does BPL play on the board?
BPL functions as the ARCNET communication link to the AAHA2 board. Similar to APL, BPL manages data transmission and communication protocols between the board and the AAHA2 board, ensuring efficient connectivity and operation for ARCNET-based functionalities within the R core.

How does P1 contribute to the functionality?
P1 serves as a bus connection point between the board and the LBC586P processor board. This connection enables data transfer and synchronization between the board and the main processor board (LBC586P), facilitating coordinated operations and system functionality across the R core system.

What is the role of P2 on the board?
P2 also functions as a bus connection to the LBC586P processor board, similar to P1. It provides an additional bus connection point that supports data exchange and synchronization between the board and the main processor board (LBC586P), enhancing overall system performance and integration.