DS215TCEAG1BZZ01A - Emergency Overspeed Board

Part Number: DS215TCEAG1BZZ01A
Manufacturer: General Electric
Series: Mark V LM
Product Type: Emergency Overspeed Board with Firmware
Availability: In Stock
Product of Origin: U.S.A
Weight:1.00 lbs
Dimensions:6.00 x 5.00 x 1.00
Manual: GEH - 6153

DS215TCEAG1BZZ01A is an Emergency Overspeed Board with EPROMS manufactured by General Electric as part of the Mark V LM Series used for the high-speed protection security located in the protective core and is frequently referred to as the Protective Processor. The X, Y, and Z processors are the three TCEA boards that make up the P1 core. Each of these boards supplies signals for automatic synchronization, flame detection, and high and low shaft speeds. The JX1 connector, which is found on the TCEA board in location one, (X), is used to scale and condition the signals before writing them over the IONET to the STCA board in the "R1" core.

The JX1 and JX2 connections through X> are used by the TCEA boards in positions three (Y>) and five (Z>) to transport information. The R1 core's I/O Engine takes information from the three TCEA boards to perform a median selection on the three values before sending the results to the Control Engine through the COREBUS. Each TCEA board sends a trip signal to a different relay, and the TCEA boards communicate emergency trip signals to the Turbine Trip Board (TCTG). Relay driver level voting is performed by the three relays on the TCTG board, and the outcome determines whether the TCTG board trips the device. Each TCEA board includes a dedicated power supply and diagnostics for that power source.

TCEA CONFIGURATION:

HARDWARE:

Hardware jumpers J1 and J31 on the TCEA board are utilized for factory testing. IONET termination resistors are used with J2 and J3. Each TCEA board's IONET address is configured using the hardware jumpers J4, J5, and J6. J12 through J21 for the high-pressure shaft and J8 through J11 and J22 through 27 for the low-pressure shaft are used to confirm the Overspeed trip frequency settings. The I/O configuration software is used to perform the actual configuration. Z always votes for a trip on emergency Overspeed due to the hardware jumpers J28 and J29. The stall timer is enabled by J30.

SOFTWARE:

The hardware jumper settings for trip frequency are computed using the IO Configuration Editor, which is also used to establish the base speed and Overspeed values for the high and low-pressure shafts. The IO Configuration Editor is used to specify the permitted values for auto-synchronization and the pulse rate data from the Ultra Violet (UV) flame detectors, as explained below.

TCEA FLAME DETECTION CIRCUITS:

• The PTBA board in the P1 core receives signals from the UV flame detectors. The JVA and JU connectors read these signals from the PTBA terminal board to the TCEB board, and the JK (JKX/Y/Z) connectors write them to the TCEA board.

• Internal algorithms are used to scale, condition, and calculate the intensity of the signals in order to identify the status of the flame. The Control Sequence Program (CSP) in the "R" core uses the flame detect signals.

• These signals are transmitted to the I/O Engine through the IONET, which then transmits them to the Control Engine. The 335 V dc is delivered to the flame detectors by JW (JWX/Y/Z).

TCEA TURBINE OVERSPEED CIRCUITS:

• The hardware jumpers validate the Overspeed settings, and the I/O configuration constants control the emergency Overspeed trip level settings. The PTBA terminal board in the "P1" core for the emergency Overspeed circuit receives the shaft speed magnetic pick-ups.

• In order to use the signals in the Control Sequence Program for primary Overspeed, the PTBA board parallels the signals to the "R1" core. The TCEA board uses I/O configuration constants to determine shaft speed.

• To identify an Overspeed trip condition, the TCEA board checks the computed shaft speeds with the I/O configuration constants trip values.

TCEA AUTOMATIC SYNCHRONISING CIRCUIT:

• The JV connector transmits the bus and generator voltages from the PTBA terminal board to the TCEB board, where the JMP connector transfers them to the TCEA board. The TCEA board's EPROMs contain embedded software that handles voltage and speed matching.

• After verifying that the generator and line voltages and frequencies are appropriate and that the differential between the line and the generator is within the bounds specified by the I/O Configuration constant, the TCEA board transmits the permission to close the breaker.

• An independent synchronization check is carried out by the STCA board, and as a result, a logic signal is sent to the TCEA board. A breaker closure can only be made possible if this logic holds true.

WOC has the largest stock of GE Mark V LM Control System Replacement Parts. We can also repair your faulty boards. WORLD OF CONTROLS can also supply unused and rebuilt backed-up with a warranty. Our team of experts is available round the clock to support your OEM needs. Our team of experts at WOC is happy to assist you with any of your automation requirements. For pricing and availability on any parts and repairs, kindly get in touch with our team by phone or email.

FREQUENTLY ASKED QUESTIONS

Where on the panel is the component located?

The component is located on the Protective Core P1.

How are the Speed and voltage matching carried out on the card?

Speed and voltage matching is carried out via embedded software in EPROMs on the TCEA board.

What is the function of the board?

It functions as high-speed protective circuitry.

How are hardware jumper settings for trip frequency computed?

The hardware jumper settings for trip frequency are computed using the IO Configuration Editor.